| ปี พ.ศ. 2558 |
| 1 |
Novel defected ground structure and two-side loading scheme for miniaturized dual-band SIW bandpass filter designs |
| ปี พ.ศ. 2557 |
| 2 |
0.77 fJ/bit/search content addressable memory using small match line swing and automated background checking scheme for variation tolerance |
| 3 |
Design and optimization of a milli-meter wave amplifier using nano-scale CMOS devices |
| 4 |
A 4 GHz 60 dB variable gain amplifier with tunable DC offset cancellation in 65 nm CMOS |
| ปี พ.ศ. 2556 |
| 5 |
A 2-D distributed power combining by metamaterial-based zero phase shifter for 60-GHz power amplifier in 65-nm CMOS |
| 6 |
Design of high-Q millimeter-wave oscillator by differential transmission line loaded with metamaterial resonator in 65-nm CMOS |
| 7 |
Sensing margin enhancement techniques for ultra-low-voltage SRAMs utilizing a bitline-boosting current and equalized bitline leakage |
| 8 |
0.6mW 6.3 GHz 40nm CMOS divide-by-2/3 prescaler using heterodyne phase-locking technique |
| 9 |
A 2-D distributed power combining by metamaterial-based zero phase shifter for 60-GHz power amplifier in 65-nm CMOS |
| 10 |
A 76 GHz oscillator by high-Q differential transmission line loaded with split ring resonator in 65-nm CMOS |
| 11 |
A compact coupling controllable elliptical filter based on multilayer LTCC |
| 12 |
A current-mode stimulator circuit with two-step charge balancing background calibration |
| 13 |
A miniaturized millimeter-wave standing-wave filtering switch with high P1dB |
| 14 |
A new millimeter-wave fixture deembedding method based on generalized cascade network model |
| 15 |
Temperature-compensated dB-linear digitally controlled variable gain amplifier with DC offset cancellation |
| 16 |
Miniaturized 3-bit phase shifter for 60 GHz phased-array in 65 nm CMOS technology |
| 17 |
A K-band high PAE wide tuning range VCO Using triple-coupled LC tanks |
| 18 |
Coupled dual LC tanks based ILFD with low injection power and compact size |
| 19 |
Design of a power-efficient CAM using automated background checking scheme for small match line swing |
| 20 |
An improved inverter-based readout scheme for low-power ISFET sensing array |
| 21 |
Modeling and layout optimization techniques for silicon-based symmetrical spiral inductors |
| 22 |
Design and analysis of wide frequency-tuning-range CMOS 60 GHz VCO by switching inductor loaded transformer |
| ปี พ.ศ. 2555 |
| 23 |
A low voltage low power highly linear CMOS quadrature mixer using transconductance cancellation technique |
| 24 |
A dividerless PLL with low power and low reference spur by aperture-phase detector and phase-to-analog converter |
| 25 |
Impact of velocity saturation and hot carrier effects on channel thermal noise model of deep sub-micron MOSFETs |
| 26 |
A low power low phase noise dual-band multiphase VCO |
| 27 |
Bidirectional diode-triggered silicon-controlled rectifiers for low-voltage ESD protection |
| 28 |
MOSFET drain current noise modeling with effective gate overdrive and junction noise |
| 29 |
Design of a Ku-band low-phase-noise VCO using the dual LC tanks |
| 30 |
A 7.9-mW 5.6-GHz digitally controlled variable gain amplifier with linearization |
| 31 |
A 160 nW 25 kS/s 9-bit SAR ADC for neural signal recording applications |
| 32 |
A super-resolution CMOS image sensor for bio-microfluidic imaging |
| 33 |
Designs of a free-space white-LED mass-storage transceiver for SD-card file transfer |
| 34 |
Radial loaded transformed radial stub for LPF stopband extension |
| 35 |
A compact size low power and wide tuning range VCO using dual-tuning LC tanks |
| 36 |
Retention time characterization and optimization of logic-compatible embedded DRAM cells |
| 37 |
Transformer based multiple coupled LC tanks for on-chip VCO design and applications |
| 38 |
Design of a low power 60GHz OOK receiver in 65nm CMOS technology |
| 39 |
A 1.2 V 2.4 GHz low spur CMOS PLL synthesizer with a gain boosted charge pump for a batteryless transceiver |
| 40 |
DGS embedded transformed radial stub for ultra-wide stopband lowpass filter |
| 41 |
Ultra-wide rejection band lowpass cell |
| 42 |
A 44-to-60GHz, 9.7dBm P1dB, 7.1% PAE power amplifier with 2D distributed power combining by metamaterial-based zero-phase-shifter in 65nm CMOS |
| 43 |
A novel Ka band sliding IF transmitter for satellite communication |
| 44 |
Transformed radial stub cell embedded resonator for high performance filter applications |
| 45 |
A cross-coupled LPF topology and design for millimeter-wave RFIC applications |
| 46 |
A 57∼66GHz CMOS voltage-controlled oscillator using tunable differential inductor |
| 47 |
An optimum RF link for implantable devices with rectification of transmission errors |
| 48 |
Low power implantable neural recording front-end |
| 49 |
A 12-GHz high output power amplifier using 0.18µm SiGe BiCMOS for low power applications |
| 50 |
A 60GHz on-chip antenna in standard CMOS silicon technology |
| 51 |
A 9.87 nW 1 kS/s 8.7 ENOB SAR ADC for implantable epileptic seizure detection microsystems |
| 52 |
A low power millimetre-wave VCO in 0.18 µm SiGe BiCMOS technology |
| 53 |
Design of quarter-wavelength resonator filters with coupling controllable paths |
| 54 |
Integrated circuits design for neural recording sensor interface |
| 55 |
Low-power high-speed dual-modulus prescaler for Gb/s applications |
| 56 |
On-chip tunable low pass filter with improved stopband using new cross coupled topology |
| 57 |
Recent progress in silicon-based millimeter-wave power amplifier |
| 58 |
Phase compensation of cascaded conductor-backed CPW periodic cells |
| 59 |
A low-power single-phase clock multiband flexible divider |
| 60 |
A high speed low power CAM with a parity bit and power-gated ML sensing |
| 61 |
A robust 900MHz RFID reader chip with RC-calibration |
| 62 |
Class-D amplifier power stage with PWM feedback loop |
| 63 |
A 96×96 1V ultra-low power CMOS image sensor for biomedical application. |
| 64 |
A 60GHz VCO with 25.8% tuning range by switching return-path in 65nm CMOS |
| 65 |
A compact multimode bandpass filter with extended stopband bandwidth |
| ปี พ.ศ. 2554 |
| 66 |
Design exploration of hybrid CMOS and memristor circuit by new modified nodal analysis |
| 67 |
A new field dependent mobility model for high frequency channel thermal noise of deep submicron RFCMOS |
| 68 |
A 0.6-V high reverse-isolation through feedback self-cancellation for single-stage noncascode CMOS LNA |
| 69 |
A dual-loop clock and data recovery circuit with compact quarter-rate CMOS linear phase detector |
| 70 |
A compact 60 GHz LTCC microstrip bandpass filter with controllable transmission zeros |
| 71 |
A DC to 14GHz fully differential amplifier for wideband low power applications |
| 72 |
Design of a hysteresis frequency lock detector for dual-loops clock and data recovery circuit |
| ปี พ.ศ. 2553 |
| 73 |
Design and analysis of ultra low power true single phase clock CMOS 2/3 prescaler |
| 74 |
A wideband low power low-noise amplifier in CMOS technology |
| 75 |
Design of a CMOS broadband transimpedance amplifier with active feedback |
| 76 |
An energy-aware CMOS receiver front end for low-power 2.4-GHz applications |
| 77 |
A DC to 4 GHz fully differential wideband digitally controlled variable gain amplifier |
| ปี พ.ศ. 2552 |
| 78 |
A weak-inversion low-power active mixer for 2.4 GHz ISM band applications |
| 79 |
Design and sensitivity analysis of a new current-mode sense amplifier for low-power SRAM |
| 80 |
Design of low-power high-speed truncation-error-tolerant adder and its application in digital signal processing |
| 81 |
A scalable RFCMOS noise model |
| 82 |
A 3-8 GHz low-noise CMOS amplifier |
| 83 |
A wideband and high rejection multimode bandpass filter using stub perturbation |
| 84 |
An enhanced low-power high-speed adder for error-tolerant application |
| 85 |
Design and performance evaluation of a low-power data-line SRAM sense amplifier |
| 86 |
High frequency drain current noise modeling in MOSFETs under sub-threshold condition |
| 87 |
Analytical high frequency channel thermal noise modeling in deep sub-micron MOSFETs |
| 88 |
Passive circuit designs toward terahertz using nanometer CMOS technology |
| 89 |
An inductor-less broadband design technique for transimpedance amplifiers |
| 90 |
A new unified model for channel thermal noise of deep sub-micron RFCMOS |
| 91 |
A low-voltage fully-integrated CMOS power amplifier for mobile WiMAX subscriber station |
| 92 |
A fully-integrated low power PAM/PPM multi-channel UWB transmitter |
| 93 |
Power-efficient explicit-pulsed dual-edge triggered sense-amplifier flip-flops |
| ปี พ.ศ. 2551 |
| 94 |
A subthreshold low-noise amplifier optimized for ultra-low-power applications in the ISM band |
| 95 |
Modeling and layout optimization of differential inductors for Silicon-based RFIC applications |
| 96 |
16.6- and 28-GHz fully integrated CMOS RF switches with improved body floating |
| 97 |
High self-resonant and area efficient monolithic transformer using novel intercoil-crossing structure for silicon RFIC |
| 98 |
Complex shaped on-wafer interconnects modeling for CMOS RFICs |
| 99 |
Fully symmetrical monolithic transformer (true 1:1) for silicon RFIC |
| 100 |
Hybrid-mode SRAM sense amplifiers : new approach on transistor sizing |
| 101 |
An 8-bit 200-MSample/s pipelined ADC with mixed-mode front-end S/H circuit |
| 102 |
An ultra-compact planar bandpass filter with open-ground spiral for wireless application |
| 103 |
Body-bootstrapped-buffer circuit for CMOS static power reduction |
| 104 |
A full current-mode sense amplifier for low-power SRAM applications |
| 105 |
An area efficient high turn ratio monolithic transformer for silicon RFIC |
| 106 |
Sub-mW multi-GHz CMOS dual-modulus prescalers based on programmable injection-locked frequency dividers |
| ปี พ.ศ. 2550 |
| 107 |
Broad-band design techniques for transimpedance amplifiers |
| 108 |
RFCMOS unit width optimization technique |
| 109 |
Sub-1 V low power wide range injection-locked frequency divider |
| 110 |
An ultra-compact hairpin band pass filter with additional zero points |
| ปี พ.ศ. 2549 |
| 111 |
A compact size coupling controllable filter with separate electric and magnetic coupling paths |
| 112 |
A 1.8-V 2.4/5.15-GHz dual-band LC VCO in 0.18-μm CMOS technology |
| 113 |
A novel CMOS low-noise amplifier design for 3.1-to 10.6-GHz ultra-wide-band wireless receivers |
| 114 |
Scalable model of on-wafer interconnects for high-speed CMOS ICs |
| 115 |
Sensitivity analysis of coupled interconnects for RFIC applications |
| 116 |
Design and optimization of the extended true single-phase clock-based prescaler |
| ปี พ.ศ. 2548 |
| 117 |
Fully integrated CMOS fractional-N frequency divider for wide-band mobile applications with spurs reduction |
| 118 |
A miniaturized silicon-based ground ring guarded patch resonator and filter |
| 119 |
Design of a low power wide-band high resolution programmable frequency divider |
| 120 |
Equivalent circuit model of on-wafer CMOS interconnects for RFICs |
| 121 |
Physical layout design optimization of integrated spiral inductors for silicon-based RFIC applications |
| 122 |
Accurate and scalable RF interconnect model for silicon-based RFIC applications |
| 123 |
Novel RF process monitoring test structure for silicon devices. |
| ปี พ.ศ. 2547 |
| 124 |
9.3–10.4-GHz-band cross-coupled complementary oscillator with low phase-noise performance |
| 125 |
RF CMOS low-phase-noise LC oscillator through memory reduction tail transistor |
| 126 |
Parasitic-compensated quadrature LC oscillator |
| ปี พ.ศ. 2546 |
| 127 |
Metallization proximity studies for copper spiral inductors on silicon |
| ปี พ.ศ. 2544 |
| 128 |
A high-speed twin-capacitor BiNMOS (TC-BiNMOS) logic circuit for single battery operation |
| 129 |
Effective channel length and external series resistance models of scaled LDD pMOSFETs operating in a Bi-MOS hybrid-mode environment |
| ปี พ.ศ. 2542 |
| 130 |
A low-power 16×16-b parallel multiplier utilizing pass-transistor logic |
| 131 |
Comments on “Negative capacitance effect in semiconductor devices” |
| 132 |
A temperature-dependent DC model for quarter-micron LDD pMOSFET’s operating in a Bi-MOS structure |
| ปี พ.ศ. 2541 |
| 133 |
A charge-trapping-based technique to design low-voltage BiCMOS logic circuits |
| ปี พ.ศ. 2540 |
| 134 |
Experimentally-based analytical model of deep-submicron LDD pMOSFET’s in a Bi-MOS hybrid-mode environment |
