| ชื่อเรื่อง | : | Design of a hysteresis frequency lock detector for dual-loops clock and data recovery circuit |
| นักวิจัย | : | Tan, Yung Sern , Yeo, Kiat Seng , Boon, Chirn Chye , Do, Manh Anh |
| คำค้น | : | DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits |
| หน่วยงาน | : | Nanyang Technological University, Singapore |
| ผู้ร่วมงาน | : | - |
| ปีพิมพ์ | : | 2554 |
| อ้างอิง | : | Tan, Y. S., Yeo, K. S., Boon, C. C., & Do, M. A. (2011). Design of a hysteresis frequency lock detector for dual-loops clock and data recovery circuit. 2011 IEEE International Conference of Electron Devices and Solid-State Circuits, pp.1-2. , http://hdl.handle.net/10220/17712 , http://dx.doi.org/10.1109/EDSSC.2011.6117638 |
| ที่มา | : | - |
| ความเชี่ยวชาญ | : | - |
| ความสัมพันธ์ | : | - |
| ขอบเขตของเนื้อหา | : | - |
| บทคัดย่อ/คำอธิบาย | : | In dual-loops clock and data recovery (CDR) circuit design, lock detector is crucial in controlling the switching within CDR loop. The setting of the frequency accuracy of lock detector is a tough task as large ppm will leads to a longer lock time for phase tracking loop and small ppm will leads to more switching time between the loops. A novel lock detector with hysteresis property is proposed in this paper. It provides two different ppms in both different conditions; a smaller ppm for in-lock condition and a larger ppm for out-of-lock condition. This paper also provides a detailed analysis of the proposed lock detector at different conditions. The proposed lock detector is simulated in 0.18- um technology and it consumes 1.1-mW at a 1.8V supply voltage. |
| บรรณานุกรม | : |
Tan, Yung Sern , Yeo, Kiat Seng , Boon, Chirn Chye , Do, Manh Anh . (2554). Design of a hysteresis frequency lock detector for dual-loops clock and data recovery circuit.
กรุงเทพมหานคร : Nanyang Technological University, Singapore. Tan, Yung Sern , Yeo, Kiat Seng , Boon, Chirn Chye , Do, Manh Anh . 2554. "Design of a hysteresis frequency lock detector for dual-loops clock and data recovery circuit".
กรุงเทพมหานคร : Nanyang Technological University, Singapore. Tan, Yung Sern , Yeo, Kiat Seng , Boon, Chirn Chye , Do, Manh Anh . "Design of a hysteresis frequency lock detector for dual-loops clock and data recovery circuit."
กรุงเทพมหานคร : Nanyang Technological University, Singapore, 2554. Print. Tan, Yung Sern , Yeo, Kiat Seng , Boon, Chirn Chye , Do, Manh Anh . Design of a hysteresis frequency lock detector for dual-loops clock and data recovery circuit. กรุงเทพมหานคร : Nanyang Technological University, Singapore; 2554.
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