| ชื่อเรื่อง | : | A low-power 16×16-b parallel multiplier utilizing pass-transistor logic |
| นักวิจัย | : | Law, C. F. , Rofail, Samir S. , Yeo, Kiat Seng |
| คำค้น | : | DRNTU::Engineering::Electrical and electronic engineering. |
| หน่วยงาน | : | Nanyang Technological University, Singapore |
| ผู้ร่วมงาน | : | - |
| ปีพิมพ์ | : | 2542 |
| อ้างอิง | : | Law, C. F., Rofail, S. S., & Yeo., K. S. (1999). A low-power 16 16-b parallel multiplier utilizing pass-transistor logic. IEEE Journal of Solid-State Circuits, 34(10), 1395-1399. , 0018-9200 , http://hdl.handle.net/10220/6009 , http://dx.doi.org/10.1109/4.792613 |
| ที่มา | : | - |
| ความเชี่ยวชาญ | : | - |
| ความสัมพันธ์ | : | IEEE journal of solid-state circuits |
| ขอบเขตของเนื้อหา | : | - |
| บทคัดย่อ/คำอธิบาย | : | This paper describes a low-power 16x16-b parallel very large scale integration multiplier, designed and fabricated using a 0.8- m double-metal double-poly BiCMOS process. In order to achieve low-power operation, the multiplier was designed utilizing mainly pass-transistor (PT) logic circuits. The inherent nonfull-swing nature of PT logic circuits were taken full advantage of, without significantly compromising the speed performance of the overall circuit implementation. New circuit implementations for the partial-product generator and the partial-product addition circuitry have been proposed, simulated, and fabricated. Experimental results showed that the worst case multiplication time of the test chip is 10.4 ns at a supply voltage of 3.3 V, and the average power dissipation is 38 mW at a frequency of 10 MHz. |
| บรรณานุกรม | : |
Law, C. F. , Rofail, Samir S. , Yeo, Kiat Seng . (2542). A low-power 16×16-b parallel multiplier utilizing pass-transistor logic.
กรุงเทพมหานคร : Nanyang Technological University, Singapore. Law, C. F. , Rofail, Samir S. , Yeo, Kiat Seng . 2542. "A low-power 16×16-b parallel multiplier utilizing pass-transistor logic".
กรุงเทพมหานคร : Nanyang Technological University, Singapore. Law, C. F. , Rofail, Samir S. , Yeo, Kiat Seng . "A low-power 16×16-b parallel multiplier utilizing pass-transistor logic."
กรุงเทพมหานคร : Nanyang Technological University, Singapore, 2542. Print. Law, C. F. , Rofail, Samir S. , Yeo, Kiat Seng . A low-power 16×16-b parallel multiplier utilizing pass-transistor logic. กรุงเทพมหานคร : Nanyang Technological University, Singapore; 2542.
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