A 1.2-V 72-Mb double data rate 3 (DDR3) SRAM achieves a data rate of 1.5 Gb/s using dynamic self-resetting circuits [5]. Single-ended main data lines halve the data line precharging power dissipation and the number of data lines. Clocks phase shifted by 0 , 90 , and 270 are generated through the proposed clock adjustment circuits. The proposed clock adjustment circuits make input data sampled with optimized setup/hold window. On-chip input termination with the linearity error of 4.1% is developed to improve signal integrity at higher data rates. A 1.2-V 1.5-Gb/s 72-Mb DDR3 SRAM is fabricated in a 0.10- m CMOS process with five metals. The cell size and the chip size are 0.845 m2 and 151.1 mm2, respectively.