Energy-delay efficient asynchronous-logic 16×16-bit pipelined multiplier based on Sense Amplifier-Based Pass Transistor Logic

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Energy-delay efficient asynchronous-logic 16×16-bit pipelined multiplier based on Sense Amplifier-Based Pass Transistor Logic

หน่วยงาน Nanyang Technological University, Singapore

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ชื่อเรื่อง	:	Energy-delay efficient asynchronous-logic 16×16-bit pipelined multiplier based on Sense Amplifier-Based Pass Transistor Logic
นักวิจัย	:	Ho, Weng-Geng , Chong, Kwen-Siong , Lin, Tong , Gwee, Bah Hwee , Chang, Joseph Sylvester
คำค้น	:	DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
หน่วยงาน	:	Nanyang Technological University, Singapore
ผู้ร่วมงาน	:	-
ปีพิมพ์	:	2555
อ้างอิง	:	Ho, W.-G., Chong, K.-S., Lin, T., Gwee, B. H., & Chang, J. S. (2012). Energy-delay efficient asynchronous-logic 16×16-bit pipelined multiplier based on Sense Amplifier-Based Pass Transistor Logic. 2012 IEEE International Symposium on Circuits and Systems, 492-495. , http://hdl.handle.net/10220/17932 , http://dx.doi.org/10.1109/ISCAS.2012.6272073
ที่มา	:	-
ความเชี่ยวชาญ	:	-
ความสัมพันธ์	:	-
ขอบเขตของเนื้อหา	:	-
บทคัดย่อ/คำอธิบาย	:	We describe an asynchronous-logic (async) 16×16-bit pipelined multiplier based on our proposed Sense Amplifier-Based Pass Transistor Logic (SAPTL) with emphases on high energy-delay efficiency. The multiplier is targeted for an async multi-core System-On-Chip (SOC). This attribute is achieved by simplifying and optimizing the NMOS pass transistor stacks and decision-making C-element, therein to reduce the circuit area overheads and transistor switchings in SAPTL. Based on the simulations (@1V, 65nm CMOS process), the async 16×16-bit pipelined multiplier based on our proposed SAPTL approach features, on average, 31% shorter delay, 21% lower energy/operation achieving a total of 46% lower energy-delay product, and 16% lesser number of transistors when compared to the reported SAPTL approaches.
บรรณานุกรม	:	APA Chicago MLA Vancouver Ho, Weng-Geng , Chong, Kwen-Siong , Lin, Tong , Gwee, Bah Hwee , Chang, Joseph Sylvester . (2555). Energy-delay efficient asynchronous-logic 16×16-bit pipelined multiplier based on Sense Amplifier-Based Pass Transistor Logic. กรุงเทพมหานคร : Nanyang Technological University, Singapore. Ho, Weng-Geng , Chong, Kwen-Siong , Lin, Tong , Gwee, Bah Hwee , Chang, Joseph Sylvester . 2555. "Energy-delay efficient asynchronous-logic 16×16-bit pipelined multiplier based on Sense Amplifier-Based Pass Transistor Logic". กรุงเทพมหานคร : Nanyang Technological University, Singapore. Ho, Weng-Geng , Chong, Kwen-Siong , Lin, Tong , Gwee, Bah Hwee , Chang, Joseph Sylvester . "Energy-delay efficient asynchronous-logic 16×16-bit pipelined multiplier based on Sense Amplifier-Based Pass Transistor Logic." กรุงเทพมหานคร : Nanyang Technological University, Singapore, 2555. Print. Ho, Weng-Geng , Chong, Kwen-Siong , Lin, Tong , Gwee, Bah Hwee , Chang, Joseph Sylvester . Energy-delay efficient asynchronous-logic 16×16-bit pipelined multiplier based on Sense Amplifier-Based Pass Transistor Logic. กรุงเทพมหานคร : Nanyang Technological University, Singapore; 2555.