This paper describes a low-power 25-kS/s successive approximation register (SAR) analog-to-digital converter (ADC) for biomedical applications. The ADC employs a novel low-energy and area-efficient tri-level switching scheme in the DAC. Compared to the conventional SAR ADC, the average switching energy and total capacitance are reduced by 97% and 75%, respectively. Asynchronous design is implemented to eliminate the conventional system clock which is N-time of sampling rate. Furthermore, a delay-based internal clock generator produces a high-speed signal which allows True Single Phase Clock (TSPC) D Flip-flop (DFF) to be used in the low-speed biomedical applications. The ADC can work between 0 to 1 MS/s. The prototype ADC fabricated in UMC 65 nm 1P6M CMOS achieves best performance at 25 kS/s with 50.1 dB SNDR and 55.3 dB SFDR. Operating at 1 V supply and 25 kS/s, the ADC consumes 281 nW and exhibits a FOM of 43.3 fJ/conversion-step. The chip die area is 145 μm × 120 μm.