TNRR : Thai National Research ระบบคลังข้อมูลงานวิจัยไทย

จำนวนงานวิจัยจำแนกรายปี

บุคคลที่เคยร่วมงานวิจัย

ความเชี่ยวชาญ

บุคคลที่เคยร่วมงานวิจัย

#	นักวิจัย	ร่วมงาน
1	Jong, Ching Chuen	7
2	Low, Jeremy Yung Shern	6
3	Zhang, Li	5
4	Tay, Thian Fatt	4
5	Qian, Hanhua	3
6	Srikanthan, Thambipillai	3
7	Zhang, Mingyan	3
8	Xu, Fei	3
9	Cohen, Avis H.	2
10	Low, Joshua Yung Lih	2
11	Zhang, Le	2
12	Yu, Hao	2
13	Chen, Shoushun	2
14	Basu, Arindam	2
15	Xu, Pengfei	2
16	Meher, Manas Ranjan	2
17	He, Yajuan	2
18	Faust, Mathias	2
19	Cui, Aijiao	2
20	Muralidharan, Ramya	2
21	Zalivaka, Siarhei S.	1
22	Wei, Wei	1
23	Ding, Jiatao	1
24	Hao Yu	1
25	Sergeichik, Vladimir V.	1
26	Ding, Weiao	1
27	Torelli, Guido	1
28	Wei Zhang	1
29	Ye, Zhi	1
30	Cabrini, Alessandro	1
31	Kong, Zhi Hui	1
32	Ivaniuk, Alexander A.	1
33	Shao, Yu	1
34	Vinod, Achutavarrier Prasad	1
35	Tahar, Sofiène	1
36	Xiao, Rui	1
37	Paplinski, Andrew P.	1
38	Juang, Tso Bing	1
39	Wei, Chi Chung	1
40	Kumm, Martin	1
41	Tang, Howard	1
42	Siek, Liter	1
43	Huang, Xiwei	1
44	Zipf, Peter	1

ปี

#	พ.ศ.	จำนวน
1	2557	9
2	2556	5
3	2555	9
4	2554	2
5	2553	1
6	2552	5
7	2551	6
8	2550	3
9	2548	5
10	2547	1
11	2546	1

ผลงานวิจัย

#	หัวเรื่อง
ปี พ.ศ. 2557
1	A blind dynamic fingerprinting technique for sequential circuit intellectual property protection
2	A pragmatic per-device licensing scheme for hardware IP cores on SRAM-based FPGAs
3	Novel design algorithm for low complexity programmable FIR filters based on extended double base number system
4	CMOS image sensor based physical unclonable function for smart phone security applications
5	A modular design of elliptic-curve point multiplication for resource constrained devices
6	Obfuscation and watermarking of FPGA designs based on constant value generators
7	Hardware Trojan detection with linear regression based gate-level characterization
8	New algorithm for signed integer comparison in four-moduli superset {2n, 2n −1, 2n +1, 2n+1−1}
9	Leakage-resilient memory-based physical unclonable function using phase change material
ปี พ.ศ. 2556
10	An efficient channel clustering and flow rate allocation algorithm for non-uniform microfluidic cooling of 3D integrated circuits
11	A new approach to the design of efficient residue generators for arbitrary moduli
12	Thermal simulator of 3D-IC with modeling of anisotropic TSV conductance and microchannel entrance effects
13	A cluster-based distributed active current sensing circuit for hardware Trojan detection
14	Efficient VLSI implementation of 2^n scaling of signed integer in RNS {2^n-1, 2^n, 2^n+1}
ปี พ.ศ. 2555
15	A VLSI efficient programmable power-of-two scaler for 2n-1, 2n,2n+1 RNS
16	An area and energy efficient inner-product processor for serial-link bus architecture
17	Area-power efficient modulo 2n-1 and modulo 2n+1 multipliers for {2n-1, 2n, 2n+1} based RNS
18	Dynamical systems guided design and analysis of silicon oscillators for central pattern generators
19	A compact 16-bit dual-slope integrating circuit for direct analog-to-residue conversion
20	A unified {2n−1, 2n, 2n+1} RNS scaler with dual scaling constants
21	Pipelined adder graph optimization for high speed multiple constant multiplication
22	State encoding watermaking for field authentication of sequential circuit intellectual property
23	A fast and compact circuit for integer square root computation based on Mitchell logarithmic method
ปี พ.ศ. 2554
24	Cyber-physical thermal management of 3D multi-core cache-processor system with microfluidic cooling
25	Dynamical systems : a tool for analysis and design of silicon half center oscillators
ปี พ.ศ. 2553
26	Evaluation Of Generic Medicines Substitution Practices Among Community Pharmacists In Malaysia And Australia
ปี พ.ศ. 2552
27	Optimization of structural adders in fixed coefficient transposed direct form FIR filters
28	High-level synthesis algorithm for the design of reconfigurable constant multiplier
29	A new redundant binary Booth encoding for fast 2^n-bit multiplier design
30	Hard multiple generator for higher radix modulo 2^n-1 multiplication
31	Area-saving technique for low-error redundant binary fixed-width multiplier implementation
ปี พ.ศ. 2551
32	IP watermarking using incremental technology mapping at logic synthesis level
33	Information theoretic approach to complexity reduction of FIR filter design
34	A power-delay efficient hybrid carry-lookahead/carry-select based redundant binary to two’s complement converter
35	Contention resolution : a new approach to versatile subexpressions sharing in multiple constant multiplications
36	High-speed and low-power serial accumulator for serial/parallel multiplier
37	Intellectual property authentication by watermarking scan chain in design-for-testability flow
ปี พ.ศ. 2550
38	A generalized time–frequency subtraction method for robust speech enhancement based on wavelet filter banks modeling of human auditory system
39	Design of low-complexity FIR filters based on signed-powers-of-two coefficients with reusable common subexpressions
40	A residue-to-binary converter for a new five-moduli set
ปี พ.ศ. 2548
41	Fuzzy-ART based adaptive digital watermarking scheme
42	Self-organizing topological tree for online vector quantization and data clustering
43	Contention resolution algorithm for common subexpression elimination in digital filter design
44	A review of 0.18-µm full adder performances for tree structured arithmetic circuits
45	New adaptive color quantization method based on self-organizing maps
ปี พ.ศ. 2547
46	Ultra low-voltage low-power CMOS 4-2 and 5-2 compressors for fast arithmetic circuits
ปี พ.ศ. 2546
47	An efficient reverse converter for the 4-moduli set {2^n -1, 2^n, 2^n + 1, 2^2n + 1} based on the new Chinese remainder theorem