Recently, there has been tremendous interest in CMOS integrated circuits for radio-frequency (RF) applications. This trend has been driven by the desire to integrate the entire RF circuitry on the same substrate on which the digital circuits are in order to reduce cost. The continuous scaling of CMOS technology has progressed sufficiently to offer device performance suitable for RF applications at GHz frequencies. The demonstration of transistors with gate lengths of 32 nm and fT’s higher than 320 GHz suggests the trend will continue throughout this decade. Nevertheless, RF designs in CMOS face some challenges that must be resolved before the “single-chip radio” can be realized. In particular, the quality of on-chip passive components is among the most pressing issues to overcome. As frequency increases the inductor’s quality factor (Q) improves while the quality factor of capacitors and varactors degrade. In This dissertation, a new CMOS-compatible varactor with low tuning voltage is introduced and modeled in detail. The varactor can achieve a tuning range of 3:1 relatively independent of supply voltage and its quality factor improves with technology scaling.

On-chip RF filter implementation is another major difficulty in CMOS RF design. Due to the low Q of on-chip spiral inductors, filter loss becomes too large. To overcome the loss, a novel Q-enhancement scheme is presented, which has been shown to achieve an effective Q as high as 170 in a 0.25-um CMOS process. Using the Q-enhancement technique, a 2.14 GHz bandpass filter is fabricated and measurement data shows 0-dB insertion loss is achieved. The filter using the Q-enhancement scheme possesses no inherent passband distortion associated with the conventional scheme, whose loss compensation element shows strong frequency dependence."