| ชื่อเรื่อง | : | Synchronization error estimation and controller design for delayed Lur'e systems with parameter mismatches |
| นักวิจัย | : | He, Wangli. , Qian, Feng. , Han, Qing-Long. , Cao, Jinde. |
| คำค้น | : | Neural networks (Computer science) , Strategic basic research. , 970101 Expanding Knowledge in the Mathematical Sciences. , 010203 Calculus of Variations, Systems Theory and Control Theory. , Synchronization. , Delayed Lur'e systems -- Neural networks -- Parameter mismatches -- Synchronization , Journal Article. Refereed, Scholarly Journal |
| หน่วยงาน | : | Central Queensland University, Australia |
| ผู้ร่วมงาน | : | - |
| ปีพิมพ์ | : | 2555 |
| อ้างอิง | : | http://hdl.cqu.edu.au/10018/937403 |
| ที่มา | : | He, W, Qian, F, Han, Ql & Cao, J 2012, 'Synchronization error estimation and controller design for delayed Lur'e systems with parameter mismatches', IEEE Transactions on Neural Networks and Learning Systems, vol. 23, no. 10, pp. 1551-1563, http://dx.doi.org/10.1109/TNNLS.2012.2205941 |
| ความเชี่ยวชาญ | : | - |
| ความสัมพันธ์ | : | IEEE transactions on neural networks and learning systems. Piscataway, NJ : IEEE, 2012. Vol. 23, no. 10 (October 2012), p. 1551-1563 13 pages Refereed 2162-237X , ACQUIRE [electronic resource] : Central Queensland University Institutional Repository. |
| ขอบเขตของเนื้อหา | : | - |
| บทคัดย่อ/คำอธิบาย | : | This paper investigates the problem of master-slave synchronization of two delayed Lur'e systems in the presence of parameter mismatches. First, by analyzing the corresponding synchronization error system, synchronization with an error level, which is referred to as quasi-synchronization, is established. Some delay-dependent quasi-synchronization criteria are derived. An estimation of the synchronization error bound is given, and an explicit expression of error levels is obtained. Second, sufficient conditions on the existence of feedback controllers under a predetermined error level are provided. The controller gains are obtained by solving a set of linear matrix inequalities. Finally, a delayed Chua's circuit is chosen to illustrate the effectiveness of the derived results. |
| บรรณานุกรม | : |
He, Wangli. , Qian, Feng. , Han, Qing-Long. , Cao, Jinde. . (2555). Synchronization error estimation and controller design for delayed Lur'e systems with parameter mismatches.
กรุงเทพมหานคร : Central Queensland University, Australia. He, Wangli. , Qian, Feng. , Han, Qing-Long. , Cao, Jinde. . 2555. "Synchronization error estimation and controller design for delayed Lur'e systems with parameter mismatches".
กรุงเทพมหานคร : Central Queensland University, Australia. He, Wangli. , Qian, Feng. , Han, Qing-Long. , Cao, Jinde. . "Synchronization error estimation and controller design for delayed Lur'e systems with parameter mismatches."
กรุงเทพมหานคร : Central Queensland University, Australia, 2555. Print. He, Wangli. , Qian, Feng. , Han, Qing-Long. , Cao, Jinde. . Synchronization error estimation and controller design for delayed Lur'e systems with parameter mismatches. กรุงเทพมหานคร : Central Queensland University, Australia; 2555.
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