Detailed experimental and two-dimensional process and device simulation of Drain induced Barrier Lowering (DIBL) effect versus channel length of NMOS with n+ polysilicon gate that fabricated at TMEC by 0.8 CMOS technology were presented. The results show the DIBL parameter become worse for the range of  0.8 m. and almost neglected for the range of L> 3.0 um. The two-dimensional device simulation program TSUPREM-4 and MEDICI, that includes process and device modeling was used to investigated this characteristics. The simulations show that the reduction the channel gate length long to short channel has a following effect(a) a shorter lateral depletion region width between source or drain and the channel and (b)the current in channel transition from surface through subsurface to bulk. Design consideration in short channel device to minimized DIBL effect such as and DIBL parameter are also briefly discussed later on.