Nonvolatile memory (NVM) technology is going through a fast evolution amongst the semiconductor technologies in the last decade. To satisfy the increasing demand of flash memory, the memory density has been continuously increased through aggressive scaling of the device dimensions in 2-dimensional (2-D) plane. However, the cell size shrinking in 2-D is getting more and more difficult beyond sub-20-nm technology node due to concerns on lithography, coupling ratio, and crosstalk interference. In order to overcome the obstacles of flash memory scaling in 2-D planar platform, a large amount of research work has been conducted so far which can be mainly classified into two categories: adoption of novel cell structures and exploration of new materials. Among various cell structures, the Gate-All-Around (GAA) cylindrical nanowire (NW)- field effect transistor (FET) is being considered as one of the strong potential candidates to advance the NVM technology to the extreme miniaturization limits, due to the optimal electrostatic control which translates into nearly ideal subthreshold turn-on and a negligibly small short channel effect (SCE). This thesis proposes methodologies to resolve issues of memory cell scaling, program/erase (P/E) speed and reliability in the Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) type discrete charge storage NVM based on a novel CMOS compatible single-crystalline vertical silicon nanowire (SiNW) platform.