Current embedded computing systems demand not only a high performance but also lower power consumption. For this reason, this research aims to build a software framework that enables a rapid design of energy-efficient embedded systems. Particularly, this research focuses on a dynamic voltage and frequency scaling (DVFS) algorithm, which has been found effective in reducing power consumption. The rationale behind DVFS is to avoid the processor being idle in high operating clock frequency and voltage. Instead, the processor can save power by running the task at a lower clock frequency and voltage, and completing it just before the real-time deadline. The latter action is necessary to ensure a constant performance quality of the application. This thesis proposes and describes a novel and effective DVFS algorithm that is suitable mostly for embedded signal processing applications. The proposed method does not require a costly estimation process that is being used in many conventional DVFS algorithms. Instead, our algorithm successfully tunes the clock frequency and voltage by exploiting the existence of fixed-length processing and variable-length processing in a typical digital signal processing application.