An output capacitorless low-dropout (LDO) regulator, which applies the proposed Dual Summed Miller Frequency Compensation (DSMFC) on Flipped Voltage Follower (FVF) structure with composite power transistor, is proposed. Validated by UMC 65nm CMOS process, the simulation results have shown that the proposed LDO regulator consumes only 13.2μA at a 1.2V supply, with a dropout voltage of 200mV. At a total of 10pF compensation capacitance, it can support 0-50mA load current for a load capacitance range of 10pF-100nF at typical process and temperature whilst 10pF-10nF at worst condition. The proposed LDO regulator is able to recover in 0.925μs at CL=50pF. The comparison results have shown that the maximum load capacitance is more than two orders of magnitude with respect to those of the FVF LDO counterparts at identical process, supply, quiescent power and compensation capacitance.