The impact of etch-stop layers (ESLs) of borderless contact (BLC) on transistor characteristics, especially for NMOSFETs, was studied concerning on the ESL-induced mechanical stress. Two new ESL schemes using dual etch-stop layers: (scheme A) SiON (bottom)/SiN (top) and (scheme B) SiN (bottom)/SiON (top) were studied and implemented into device fabrication. The electrical performance of the N- and PMOSFETs was characterized. It has been found that by using scheme A, a 2.7% improvement of Ion versus Ioff margin as compared with the single-layer process is achieved on NMOSFETs. The scheme A results in a loss of the PMOS margin by 1.4%, which is still within the specifications. However, scheme B, which uses a SiN as the bottom layer, presents a slightly less improvement of process margin (1.7%) on NMOSFETs with much larger loss of process margin (2.3%) on PMOSFETs. Our results suggest that optimization of ESL for borderless contact could play an important role in determining transistor performance for deep submicron CMOS.