Offset error mechanisms in a single-ended chopperstabilized amplifier are investigated. The error models and their prediction equations are given. This work also presents a new analytical approach for estimating the switch error in a four-transistor chopping network. A new resistance balancing circuit technique is also introduced, which permits further reduction of dc offsets in conventional chopping operational amplifier (op-amp) or chopping differential difference amplifier (DDA). The HSPICE simulation results have validated the proposed technique and identified dominant error sources using Level-49 BSIM3 model in a standard 0.6-µm CMOS technology. Applying the technique to the fabricated DDA chips at a noninverting gain of ten and a single 3-V supply, the measured results have shown that 40% of the ten samples display no more than 3- and 5-µV offsets at the chopping frequency of 10 and 64 kHz, respectively. The proposed technique offers a potential advantage for improving the yield of low-offset amplifiers in sensory systems.