In this thesis, low-frequency noise (LFN) mechanisms of multiple-gate transistors are investigated. The first-time observations and analyses, together with necessary modifications or re-derivations of LFN model equations, provide important guidance for multiple-gate transistor circuit designs and multiple-gate MOS technology optimizations. Performing meaningful LFN measurements in the presence of undesired disturbances from electronic equipments is always a difficult task. A floating-gate (FG) test structure that constructs the characterized MOSFET with an extra control gate is proposed for the MOS transistors. By using this test structure, no gate bias is required in the drain-current noise measurement. As a result, any potential disadvantages from gate-bias supply networks that would prevent accurate noise measurements are totally excluded. It is also the first experimental demonstration in MOS technology for the joint effect of a backgating noise and an instrumental disturbance observed in planar resistors. The FinFET and the nanowire transistor are both important candidates for future CMOS scaling beyond the 32-nm node.