TNRR : Thai National Research ระบบคลังข้อมูลงานวิจัยไทย

จำนวนงานวิจัยจำแนกรายปี

บุคคลที่เคยร่วมงานวิจัย

ความเชี่ยวชาญ

บุคคลที่เคยร่วมงานวิจัย

#	นักวิจัย	ร่วมงาน
1	Kim, Chris H.	7
2	Do, Anh Tuan	6
3	Pott, Vincent	5
4	Yeo, Kiat Seng	4
5	Lin, Julius Tsai Ming	4
6	Chua, Geng Li	4
7	Keane, John.	3
8	Vaddi, Ramesh.	3
9	Yin, Chun	2
10	Dasgupta, Sudeb.	2
11	Agarwal, Rajendra P.	2
12	Eom, Hanyong.	2
13	Aung, Myat Thu Linn	1
14	Lim, Eric	1
15	Li, Qi	1
16	Ho, Kim Ming	1
17	Tsai, Julius Ming-Lin	1
18	Kong, Zhi Hui	1
19	Yoshikawa, Takefumi	1
20	Gopal, Jayaraman Karthik	1
21	Singh, Pushpapraj	1
22	Zhou, Jun	1
23	Velayudhan, Kavitha	1
24	Wang, Jian-Ping	1
25	Harms, Jonathan D.	1
26	Yu, Xiangyao	1
27	Zhao, Hui	1
28	Yeoh, Yuan Lin	1
29	Lee, Kwang Jin	1
30	Bae, Dae Gi	1
31	Kim, Nam Seog	1
32	Kim, Kang Young	1
33	Yoon, Yong-Jin	1
34	Cho, Uk Rae	1
35	Sapatnekar, Sachin.	1
36	Persaud, Randy.	1
37	Yang, Jeong Suk	1
38	Sohn, Kwon Il	1
39	Byun, Hyun Geun	1
40	Nguyen, Truc Quynh	1
41	Ahn, Kee Sik	1
42	Kim, Su Chul	1
43	Lee, In Yeol	1
44	Kang, Tae Gyoung	1
45	Yi, He	1

ปี

#	พ.ศ.	จำนวน
1	2557	1
2	2556	5
3	2555	12
4	2554	3
5	2552	1
6	2551	3
7	2550	1
8	2546	1

ผลงานวิจัย

#	หัวเรื่อง
ปี พ.ศ. 2557
1	0.77 fJ/bit/search content addressable memory using small match line swing and automated background checking scheme for variation tolerance
ปี พ.ศ. 2556
2	Sensing margin enhancement techniques for ultra-low-voltage SRAMs utilizing a bitline-boosting current and equalized bitline leakage
3	A 0.4V 7T SRAM with write through virtual ground and ultra-fine grain power gating switches
4	A scaling roadmap and performance evaluation of in-plane and perpendicular MTJ based STT-MRAMs for high-density cache memory
5	Design and array implementation a cantilever-based non-volatile memory utilizing vibrational reset
6	Design of a power-efficient CAM using automated background checking scheme for small match line swing
ปี พ.ศ. 2555
7	Design and scalability of a memory array utilizing anchor-free nanoelectromechanical nonvolatile memory device
8	Design optimization of pulsed-mode electromechanical nonvolatile memory
9	Retention time characterization and optimization of logic-compatible embedded DRAM cells
10	Maximization of SRAM energy efficiency utilizing MTCMOS technology
11	The shuttle nanoelectromechanical nonvolatile memory
12	High energy efficient ultra-low voltage SRAM design : device, circuit, and architecture
13	NBTI/PBTI-aware wordline voltage control with no boosted supply for stability improvement of half-selected SRAM cells
14	A 5.61 pJ, 16 kb 9T SRAM with single-ended equalized bitlines and fast local write-back for cell stability improvement
15	Design and analysis of anchorless shuttle nano-electro-mechanical non-volatile memory for high temperature applications
16	Design of simultaneous bi-directional transceivers utilizing capacitive coupling for 3DICs in face-to-face configuration
17	Design of ring oscillator structures for measuring isolated NBTI and PBTI.
18	Design, modeling and simulation of an anchorless nano-electro- mechanical nonvolatile memory
ปี พ.ศ. 2554
19	Design and analysis of double-gate MOSFETs for ultra-low power radio frequency identification (RFID) : device and circuit co-design.
20	Ultra-low power high efficient rectifiers with 3T/4T double-gate MOSFETs for RFID applications.
21	Design and analysis of double-gate MOSFETs for ultra-low power radio frequency identification (RFID) : device and circuit co-design.
ปี พ.ศ. 2552
22	A voltage scalable 0.26 V, 64 kb 8T SRAM with Vmin lowering techniques and deep sleep mode.
ปี พ.ศ. 2551
23	Stack sizing for optimal current drivability in subthreshold circuits.
24	Silicon odometer : an on-chip reliability monitor for measuring frequency degradation of digital circuits.
25	A 0.2 V, 480 kb subthreshold SRAM with 1 k cells per bitline for ultra-low-voltage computing.
ปี พ.ศ. 2550
26	Utilizing reverse short-channel effect for optimal subthreshold circuit design.
ปี พ.ศ. 2546
27	A 1.2-V 1.5-Gb/s 72-Mb DDR3 SRAM